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connection diagram plastic dip (n), small outline (r) and cerdip (q) packages rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a high speed, low power monolithic op amp ad847 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features superior performance high unity gain bw: 50 mhz low supply current: 5.3 ma high slew rate: 300 v/ m s excellent video specifications 0.04% differential gain (ntsc and pal) 0.19 8 differential phase (ntsc and pal) drives any capacitive load fast settling time to 0.1% (10 v step): 65 ns excellent dc performance high open-loop gain 5.5 v/mv (r load = 1 k v ) low input offset voltage: 0.5 mv specified for 6 5 v and 6 15 v operation available in a wide variety of options plastic dip and soic packages cerdip package die form mil-std-883b processing tape & reel (eia-481a standard) dual version available: ad827 (8 lead) enhanced replacement for lm6361 replacement for ha2544, ha2520/2/5 and el2020 applications video instrumentation imaging equipment copiers, fax, scanners, cameras high speed cable driver high speed dac and flash adc buffers product description the ad847 represents a breakthrough in high speed amplifiers offering superior ac & dc performance and low power, all at low cost. the excellent dc performance is demonstrated by its 5 v 6 4 020 5.5 4.5 5 5 10 15 supply voltage ? volts quiescent current ?ma quiescent current vs. supply voltage specifications which include an open-loop gain of 3500 v/v (500 w load) and low input offset voltage of 0.5 mv. com mon- mode rejection is a minimum of 78 db. output voltage swing is 3 v into loads as low as 150 w . analog devices also offers over 30 other high speed amplifiers from the low noise ad829 (1.7 nv/ ? hz ) to the ultimate video amplifier, the ad811, which features 0.01% differential gain and 0.01 differential phase. application highlights 1. as a buffer the ad847 offers a full-power bandwidth of 12.7 mhz (5 v p-p with 5 v supplies) making it outstand- ing as an input buffer for flash a/d converters. 2. the low power and small outline package of the ad847 make it very well suited for high density applications such as multiple pole active filters. 3. the ad847 is internally compensated for unity gain opera- tion and remains stable when driving any capacitive load. ad847 driving capacitive loads
ad847Cspecifications rev. f C2C (@ t a = +25 8 c, unless otherwise noted) model ad847j ad847ar conditions v s min typ max min typ max units input offset voltage 1 5 v 0.5 1 0.5 1 mv t min to t max 3.5 4 mv offset drift 15 15 m v/ c input bias current 5 v, 15 v 3.3 6.6 3.3 6.6 m a t min to t max 7.2 10 m a input offset current 5 v, 15 v 50 300 50 300 na t min to t max 400 500 na offset current drift 0.3 0.3 na/ c open-loop gain v out = 2.5 v 5 v r load = 500 w 2 3.5 2 3.5 v/mv t min to t max 1 1 v/mv r load = 150 w 1.6 1.6 v/mv v out = 10 v 15 v r load = 1 k w 3 5.5 3 5.5 v/mv t min to t max 1.5 1.5 v/mv dynamic performance unity gain bandwidth 5 v 35 35 mhz 15 v 50 50 mhz full power bandwidth 2 v out = 5 v p-p r load = 500 w , 5 v 12.7 12.7 mhz v out = 20 v p-p, r load = 1 k w 15 v 4.7 4.7 mhz slew rate 3 r load = 1 k w 5 v 200 200 v/ m s 15 v 225 300 225 300 v/ m s settling time to 0.1%, r load = 250 w C2.5 v to +2.5 v 5 v 65 65 ns 10 v step, a v = C1 15 v 65 65 ns to 0.01%, r load = 250 w C2.5 v to +2.5 v 5 v 140 140 ns 10 v step, a v = C1 15 v 120 120 ns phase margin c load = 10 pf 15 v r load = 1 k w 50 50 degree differential gain f ? 4.4 mhz, r load = 1 k w 15 v 0.04 0.04 % differential phase f ? 4.4 mhz, r load = 1 k w 15 v 0.19 0.19 degree common-mode rejection v cm = 2.5 v 5 v 78 95 78 95 db v cm = 12 v 15 v 78 95 78 95 db t min to t max 75 75 db power supply rejection v s = 5 v to 15 v 75 86 75 86 db t min to t max 72 72 db input voltage noise f = 10 khz 15 v 15 15 nv/ ? hz input current noise f = 10 khz 15 v 1.5 1.5 pa/ ? hz input common-mode voltage range 5 v +4.3 +4.3 v C3.4 C3.4 v 15 v +14.3 +14.3 v C13.4 C13.4 v output voltage swing r load = 500 w 5 v 3.0 3.6 3.0 3.6 v r load = 150 w 5 v 2.5 3 2.5 3 v r load = 1 k w 15 v 12 12 v r load = 500 w 15 v 10 10 v short-circuit current 15 v 32 32 ma input resistance 300 300 k w input capacitance 1.5 1.5 pf output resistance open loop 15 15 w power supply operating range 6 4.5 6 18 6 4.5 6 18 v quiescent current 5 v 4.8 6.0 4.8 6.0 ma t min to t max 7.3 7.3 ma 15 v 5.3 6.3 5.3 6.3 ma t min to t max 7.6 7.6 ma n otes l input offset voltage specifications are guaranteed after 5 minutes at t a = +25 c. 2 full power bandwidth = slew rate/2 p v peak . 3 slew rate is measured on rising edge. all min and max specifications are guaranteed. specifications in boldface are 100% tested at final electrical test. specifications subject to change without notice.
ad847 rev. f C3C model ad847aq ad847s conditions v s min typ max min typ max units input offset voltage 1 5 v 0.5 1 0.5 1 mv t min to t max 44 mv offset drift 15 15 m v/ c input bias current 5 v, 15 v 3.3 5 3.3 5 m a t min to t max 7.5 7.5 m a input offset current 5 v, 15 v 50 300 50 300 na t min to t max 400 400 na offset current drift 0.3 0.3 na/ c open-loop gain v out = 2.5 v 5 v r load = 500 w 2 3.5 2 3.5 v/mv t min to t max 11 v/mv r load = 150 w 1.6 1.6 v/mv v out = = 10 v 15 v r load = 1 k w 3 5.5 3 5.5 v/mv t min to t max 1.5 1.5 v/mv dynamic performance unity gain bandwidth 5 v 35 35 mhz 15 v 50 50 mhz full power bandwidth 2 v out = 5 v p-p r load = 500 w , 5 v 12.7 12.7 mhz v out = 20 v p-p, r load = 1 k w 15 v 4.7 4.7 mhz slew rate 3 r load = 1 k w 5 v 200 200 v/ m s 15 v 225 300 225 300 v/ m s settling time to 0.1%, r load = 250 w C2.5 v to +2.5 v 5 v 65 65 ns 10 v step, a v = C1 15 v 65 65 ns to 0.01%, r load = 250 w C2.5 v to +2.5 v 5 v 140 140 ns 10 v step, a v = C1 15 v 120 120 ns phase margin c load = 10 pf 15 v r load = 1 k w 50 50 degree differential gain f ? 4.4 mhz, r load = 1 k w 15 v 0.04 0.04 % differential phase f ? 4.4 mhz, r load = 1 k w 15 v 0.19 0.19 degree common-mode rejection v cm = 2.5 v 5 v 80 95 80 95 db v cm = 12 v 15 v 80 95 80 95 db t min to t max 75 75 db power supply rejection v s = 5 v to 15 v 75 86 75 86 db t min to t max 72 72 db input voltage noise f = 10 khz 15 v 15 15 nv/ ? hz input current noise f = 10 khz 15 v 1.5 1.5 pa/ ? hz input common-mode voltage range 5 v +4.3 +4.3 v C3.4 C3.4 v 15 v +14.3 +14.3 v C13.4 C13.4 v output voltage swing r load = 500 w 5 v 3.0 3.6 3.0 3.6 v r load = 150 w 5 v 2.5 3 2.5 3 v r load = 1 k w 15 v 12 12 v r load = 500 w 15 v 10 10 v short-circuit current 15 v 32 32 ma input resistance 300 300 k w input capacitance 1.5 1.5 pf output resistance open loop 15 15 w power supply operating range 6 4.5 6 18 6 4.5 6 18 v quiescent current 5 v 4.8 5.7 4.8 5.7 ma t min to t max 7.0 7.8 ma 15 v 5.3 6.3 5.3 6.3 ma t min to t max 7.6 8.4 ma
ad847 rev. f C4C absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 plastic (n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 watts small outline (r) . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 watts cerdip (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 watts input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . 6 v storage temperature range (q) . . . . . . . . . C65 c to +150 c (n, r) . . . . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +125 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175 c lead temperature range (soldering 60 sec) . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 mini-dip package: q ja = 100 c/watt; q jc = 33 c/watt cerdip package: q ja = 110 c/watt; q jc = 30 c/watt small outline package: q ja = 155 c/watt; q jc = 33 c/watt esd susceptibility esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 volts, which readily accumulate on the human body and on test equipment, can discharge without de- tection. although the ad847 features proprietary esd protec- tion circuitry, permanent damage may still occur on these devices if they are subjected to high energy electrostatic dis- charges. therefore, proper esd precautions are recommended to avoid any performance degradation or loss of functionality. metalization photograph contact factory for latest dimensions. dimensions shown in inches and (mm). ordering guide temperature package package models* range C 8 c description option ad847jn 0 to +70 plastic n-8 ad847jr 0 to +70 soic r-8 ad847aq C40 to +85 cerdip q-8 ad847ar C40 to +85 soic r-8 ad847sq C55 to +125 cerdip q-8 ad847sq/883b C55 to +125 cerdip q-8 5962-8964701pa C55 to +125 cerdip q-8 *ad847 also available in j and s grade chips, and ad847jr and ad847ar are available * in tape and reel.
ad847 rev. f C5C typical characteristics (@ +25 8 c and v s = 6 15 v, unless otherwise noted) 20 0 020 15 5 5 10 10 15 input common-mode range ? volts supply voltage ? volts ? in +v in figure 1. input common-mode range vs. supply voltage 15 v supplies 30 0 10k 15 5 100 10 10 20 1k 25 load resistance ? w output voltage swing ?volts p-p 5v supplies figure 3. output voltage swing vs. load resistance ?0 140 ?0 120 100 80 60 40 20 0 ?0 5 4 3 2 temperature ? c input bias current ? m a v = 5v s figure 5. input bias current vs. temperature 20 0 020 15 5 5 10 10 15 supply voltage ? volts output voltage swing ?volts +v out ? out r = 500 w load figure 2. output voltage swing vs. supply voltage 6 4 020 5.5 4.5 5 5 10 15 supply voltage ? volts quiescent current ?ma figure 4. quiescent current vs. supply voltage 100 0.01 10k 100m 10 0.1 100k 1 1m 10m frequency ?hz output impedance ? w figure 6. output impedance vs. frequency
ad847Ctypical characteristics (@ +25 8 c and v s = 6 15 v, unless otherwise noted) rev. f C6C 35 15 140 20 ?0 ?0 25 30 120 100 80 60 40 20 0 ?0 ambient temperature ? c short circuit current limit ?ma figure 8. short-circuit current limit vs. temperature 100 ?0 100m 40 0 1k 20 100 80 60 10m 1m 100k 10k +100 +80 +60 +40 +20 0 phase margin ?degrees frequency ?hz open -loop gain ?db 15v supplies 5v supplies 1k w load 500 w load figure 10. open-loop gain and phase margin vs. frequency 100 0 100m 60 20 10k 40 1k 80 10m 1m 100k +supply ?upply frequency ?hz power supply rejection ?db figure 12. power supply rejection vs. frequency 7 3 140 4 ?0 ?0 5 6 120 100 80 60 40 20 0 ?0 temperature ? c quiescent current ?ma v = 5v s figure 7. quiescent current vs. temperature 52 48 ?0 140 51 49 ?0 50 100 120 80 60 40 20 0 ?0 temperature ? c unity ?gain bandwidth ?mhz figure 9. gain bandwidth product vs. temperature 80 50 10k 65 55 100 60 10 75 70 1k v = 5v s v = 15v s load resistance ? w open-loop gain ?db figure 11. open-loop gain vs. load resistance
ad847 rev. f C7C 30 0 100m 15 10m 10 1m 25 20 5 input frequency ?hz output voltage ?volts p? r = 1k w l figure 14. large signal frequency response ?0 ?30 100 100k ?0 ?10 1k 10k ?0 ?00 ?20 harmonic distortion ?db frequency ?hz 3v rms r =1k w l 2nd harmonic 3rd harmonic figure 16. harmonic distortion vs. frequency 450 150 140 300 200 ?0 250 ?0 400 350 120 80 60 40 100 20 0 ?0 temperature ? c slew rate ?v/ m s figure 18. slew rate vs. temperature 100 0 100m 60 20 10k 40 1k 80 10m 1m 100k frequency ?hz cmr ?db v = 1v p-p cm figure 13. common-mode rejection vs. frequency 10 ?0 160 ? ? 20 ? 0 2 ? 0 4 6 8 140 120 100 80 60 40 output swing from 0 to v settling time ?ns 1% 0.1% 1% 0.1% figure 15. output swing and error vs. settling time 50 0 10m 30 10 100 20 10 40 1m 100k 10k 1k frequency ?hz input voltage noise ?nv/ hz figure 17. input voltage noise spectral density
ad847 rev. f C8C figure 19. inverting amplifier configuration figure 19a. inverter large signal pulse response figure 19b. inverter small signal pulse response figure 20. noninverting amplifier configuration figure 20a. noninverting large signal pulse response figure 20b. noninverting small signal pulse response
ad847 rev. f C9C offset nulling the input offset voltage of the ad847 is very low for a high speed op amp, but if additional nulling is required, the circuit shown in figure 21 can be used. figure 21. offset nulling input considerations an input resistor (r in in figure 20) is required in circuits where the input to the ad847 will be subjected to transient or con- tinuous overload voltages exceeding the 6 v maximum differ- ential limit. this resistor provides protection for the input transistors by limiting the maximum current that can be forced into their bases. for high performance circuits it is recommended that a resistor (r b in figures 19 and 20) be used to reduce bias current errors by matching the impedance at each input. the offset voltage er- ror will be reduced by more than an order of magnitude. theory of operation the ad847 is fabricated on analog devices proprietary complementary bipolar (cb) process which enables the con- struction of pnp and npn transistors with similar f t s in the 600 mhz to 800 mhz region. the ad847 circuit (figure 22) includes an npn input stage followed by fast pnps in the folded cascode intermediate gain stage. the cb pnps are also used in the current amplifying output stage. the internal compensation capacitance that makes the ad847 unity gain stable is provided by the junction capacitances of transistors in the gain stage. the capacitor, c f , in the output stage mitigates the effect of ca- pacitive loads. at low frequencies and with low capacitive loads, the gain from the compensation node to the output is very close to unity. in this case c f is bootstrapped and does not contribute to the compensation capacitance of the part. as the capacitive load is increased, a pole is formed with the output impedance of the output stage. this reduces the gain, and therefore, c f is incompletely bootstrapped. some fraction of c f contributes to the compensation capacitance, and the unity gain bandwidth falls. as the load capacitance is increased, the band- width continues to fall, and the amplifier remains stable. c f ?n +in null 1 null 8 output +v s ? s figure 22. ad847 simplified schematic grounding and bypassing in designing practical circuits with the ad847, the user must remember that whenever high frequencies are involved, some special precautions are in order. circuits must be built with short interconnect leads. a large ground plane should be used whenever possible to provide a low resistance, low inductance circuit path, as well as minimizing the effects of high frequency coupling. sockets should be avoided because the increased interlead capacitance can degrade bandwidth. feedback resistors should be of low enough value to assure that the time constant formed with the capacitance at the amplifier summing junction will not limit the amplifier performance. resistor values of less than 5 k w are recommended. if a larger resistor must be used, a small (<10 pf) feedback capacitor in parallel with the feedback resistor, r f , may be used to compen- sate for the input capacitances and optimize the dynamic perfor- mance of the amplifier. power supply leads should be bypassed to ground as close as possible to the amplifier pins. ceramic disc capacitors of 0.1 m f are recommended.
ad847 rev. f C10C video line driver the ad847 functions very well as a low cost, high speed line driver for either terminated or unterminated cables. figure 23 shows the ad847 driving a doubly terminated cable in a fol- lower configuration. the termination resistor, r t , (when equal to the cables charac- teristic impedance) minimizes reflections from the far end of the cable. while operating from 5 v supplies, the ad847 main- tains a typical slew rate of 200 v/ m s, which means it can drive a 1 v, 30 mhz signal into a terminated cable. 0.1 m f 0.1 m f 500 w 500 w 75 w ad847 75 w 75 w r t r bt c c see table i +v s v in v out ? s in r 100 w 75 w coax 75 w coax figure 23. video line driver table i. video line driver performance chart over- v in *v supply c c C3 db b w shoot 0 db or 500 mv step 15 20 pf 23 mhz 4% 0 db or 500 mv step 15 15 pf 21 mhz 0% 0 db or 500 mv step 15 0 pf 13 mhz 0% 0 db or 500 mv step 5 20 pf 18 mhz 2% 0 db or 500 mv step 5 15 pf 16 mhz 0% 0 db or 500 mv step 5 0 pf 11 mhz 0% *C3 db bandwidth numbers are for the 0 dbm signal input. overshoot numbers are the percent overshoot of the 1 volt step input. a back-termination resistor (r bt , also equal to the characteristic impedance of the cable) may be placed between the ad847 out- put and the cable input, in order to damp any reflected signals caused by a mismatch between r t and the cables characteristic impedance. this will result in a flatter frequency response, al- though this requires that the op amp supply 2 v to the output in order to achieve a 1 v swing at resistor r t . figure 24 shows the ad847 driving 100 pf and 1000 pf loads. figure 24. ad847 driving capacitive loads flash adc input buffer the 35 mhz unity gain bandwidth of the ad847 makes it an excellent choice for buffering the input of high speed flash a/d converters, such as the ad9048. figure 25 shows the ad847 as a unity inverter for the input to the ad9048. ad9048 50 w 1.5k w 10k w 2k 0.1 0.1 100 27 2n3906 ad741 5 0.1 m f r b r t v in v cc ad847 1.5k w v ee analog input (0v to +2v) ttl convert signal 0.1 m f 0.1 m f ?.2v +5.0v convert d1 (msb) d8 (lsb) ?.2v 43 w 1k 1k ad589 figure 25. flash adc input buffer
ad847 rev. f C11C a high speed, three op-amp in-amp the circuit of figure 26 lends itself well to ccd imaging and other video speed applications. it uses two high speed cb pro- cess op-amps: amplifier a3, the output amplifier, is an ad847. the input amplifier (a1 and a2) is an ad827, which is a dual version of the ad847. this circuit has the optional flexibility of both dc and ac trims for common-mode rejection, plus the abil- ity to adjust for minimum settling time. pin 7 ad847, pin 8 ad827 1 m f 1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f each amplifier +15v ?5v comm +v s ? s 10 m f 10 m f pin 4 ad847 & ad827 ad847 2?pf settling time ac cmr adjust 2k w 1.87k w 2k w 2k w 5pf r g v out 200 w dc cmr adjust 2k w r l circuit gain = + 1 2000 w g r in +v 2 3 1 a1 1/2 ad827 1k w ? in 6 5 7 a2 1/2 ad827 1k w 2 3 6 a3 100hz 1khz 10khz 100khz 1mhz 88.3db 87.4db 86.2db 67.4db 47.1db input frequency cmrr thd + noise below input level @ 10khz 1 2 10 100 open 2k w 226 w 20 w 2? 2? 2? 2? 16.1mhz 14.7mhz 4.5mhz 660khz 200ns 200ns 370ns 2.5 m s 82db 82db 81db 71db gain r g small signal bandwidth settling time to 0.1% c (pf) adj bandwidth, settling time and total harmonic distortion vs. gain figure 26. a high speed in-amp circuit for data acquisition
ad847 rev. f C12C c1191fC10C9/92 printed in u.s.a. high speed dac buffer the wide bandwidth and fast settling time of the ad847 makes it a very good output buffer for high speed current-output d/a converters like the ad668. as shown in figure 27, the op amp establishes a summing node at ground for the dac output. the output voltage is determined by the amplifiers feedback resistor (10.24 v for a 1 k w resistor). note that since the dac gener- ates a positive current to ground, the voltage at the amplifier output will be negative. a 100 w series resistor between the noninverting amplifier input and ground minimizes the offset effects of op amp input bias currents. 1 2 3 7 24 23 22 18 8 9 10 17 16 15 11 12 14 13 4 5 21 20 6 19 ad668 +15v 10 m f to analog ground plane 0.1 m f + 1v nominal reference input 10k 1k 100 w ad847 analog ground plane analog output analog supply ground 0.1 m f 10 m f ?5v +5v 1k w 100pf digital inputs msb lsb v refcom refin1 refin2 r acom lcom ibpo v thcom vth ee load out cc i figure 27. high speed dac buffer outline dimensions dimensions shown in inches and (mm). all brand or product names mentioned are trademarks or registered trademarks of their respective holders. cerdip (q-8) package 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 15 0 0.005 (0.13) min 0.055 (1.40) max 1 pin 1 4 5 8 0.310 (7.87) 0.220 (5.59) 0.405 (10.29) max 0.200 (5.08) max seating plane 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc mini-dip (n-8) package 0.011?.003 (0.28?.08) 0.30 (7.62) ref 15 0 pin 1 4 5 8 1 0.25 (6.35) 0.31 (7.87) 0.10 (2.54) bsc seating plane 0.035?.01 (0.89?.25) 0.18?.03 (4.57?.76) 0.033 (0.84) nom 0.018?.003 (0.46?.08) 0.125 (3.18) min 0.165?.01 (4.19?.25) 0.39 (9.91) max small outline (r-8) package 0.019 (0.48) 0.014 (0.36) 0.050 (1.27) bsc 0.102 (2.59) 0.094 (2.39) 0.197 (5.01) 0.189 (4.80) 0.010 (0.25) 0.004 (0.10) 0.098 (0.2482) 0.075 (0.1905) 0.190 (4.82) 0.170 (4.32) 0.030 (0.76) 0.018 (0.46) 10 0 0.090 (2.29) 8 0 0.020 (0.051) x 45 chamf 1 8 5 4 pin 1 0.157 (3.99) 0.150 (3.81) 0.244 (6.20) 0.228 (5.79) 0.150 (3.81)

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